The invention is directed to a digital 2-of-3 selection and output circuit wherein three separate data channels are supplied in couples to logic gates in cyclic permutation. These logic gates are followed by an OR gate as an output element.
The OR gate outputs the logical result of at least two of three data channels or, respectively, data processing systems. A signal at level "1" thus always arises at the output of the OR gate when at least two of the three data channels supply a signal at level "1". One data channel can thus be down and thus offer a result deviating from the remaining two other data channels without blocking the output of the signal at level "1". When, by contrast, at least two data channels carry a signal at level "0", then the output of the OR gate also carries a signal at level "0". Such selection or, respectively, output circuits are known and described, for example, in Edgar Dombrowski, "Einfuhrung in die Zuverlassigkeit elektronischer Gerate und Systeme, AEG-Telefunken-Fachbuch 1970," pages 208/209, or by Masters U.S. Pat. No. 3,544,778. These known circuits are generally employed in safety switching units, for example in railroad signal technology. Critical parts of data processing and control systems are thereby tripled in accord with the high safety requirements, and also in view of greater availability. The same information is processed in all three of the data channels formed in this way. The digital 2-of-3 selection and output circuit serves the purpose of combining the 3 data channels.